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19-5096; Rev 0; 2/10
280MHz to 450MHz Programmable ASK/FSK Transmitter
General Description
The MAX7060 frequency and power-programmable ASK/FSK transmitter operates at 280MHz to 450MHz frequencies. This device incorporates a fully integrated fractional-N synthesizer, which allows the user to set the RF operating frequency to a large fraction of the 280MHz to 450MHz frequency range with a single crystal. For example, the MAX7060 can be tuned from 285MHz to 420MHz with a 15MHz crystal. The RF output power is user-controlled between +14dBm and -14dBm, with a 5V supply or with battery voltages as low as 3.2V. At the minimum specified battery voltage of 2.1V, the RF output power-control range is between +10dBm and -14dBm. To maintain a good output power match across a broad range of frequencies, the MAX7060 also contains a programmable matching capacitor connected in parallel with the power amplifier (PA) output. ASK modulation is accomplished by switching the PA on and off, so excellent modulation (on/off) ratios are achieved. ASK amplitude shaping is available to reduce the width of the transmission spectrum. FSK modulation is accomplished by changing the coefficients of the high-resolution fractional-N synthesizer, so FSK deviation is extremely accurate. Data rates up to 50kbps Manchester coded for ASK and 70kbps Manchester coded for FSK can be maintained while still satisfying regulatory emission-bandwidth standards. The full set of configuration functions are handled by an on-chip serial peripheral interface (SPIK). There is also a manual mode where a limited number of settings can be made directly through selected pins. The startup time is very short, and data can be transmitted 250Fs after the enable command. The MAX7060 operates from a 2.1V to 3.6V supply, or internal regulators can be used for supply voltages between 4.5V and 5.5V. The standby current in the 3V mode is 400nA at room temperature, and can be reduced to 5nA using the low-power shutdown (LSHDN) pin. The MAX7060 is available in a 24-pin (4mm x 4mm) thin QFN package and is specified for the automotive temperature range from -40NC to +125NC.
Features
S Fully Integrated, Fast Fractional-N PLL
MAX7060
280MHz to 450MHz RF Frequency Frequency Range 100% Tested at +125NC < 250s Startup Time Adjustable FSK Mark and Space Frequencies Ultra-Clean FSK Modulation 50kbps Manchester Data Rate ASK 70kbps Manchester Data Rate FSK
S Programmable Power Amplifier
+14dBm Tx Power with 5V Supply +10dBm Tx Power at 2.1V Supply 28dB Power-Control Range in 1dB Steps
S Tunable PA Matching Capacitor S Control Through SPI or Manual Settings S Low Shutdown Current for 2.1V to 3.6V Supply
400nA Standby Current, Power-On-Reset (POR) Active 5nA Shutdown Current, POR Inactive
S Supply Flexibility
2.1V to 3.6V Single-Supply Operation or 4.5V to 5.5V Supply Operation with Internal Regulators
S 24-Pin (4mm x 4mm) TQFN Package S FCC Part 15, ETSI EN 300 220 Compliant*
*ETSI compliance up to +6dBm EIRP.
Applications
Garage-Door Openers Remote Controls Home and Industrial Automation Sensor Networks Security Systems
Ordering Information
PART MAX7060ATG+ TEMP RANGE -40NC to +125NC PIN-PACKAGE 24 TQFN-EP*
MAX7060ATG/V+ -40NC to +125NC 24 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. /V denotes an automotive qualified part. *EP = Exposed pad.
SPI is a trademark of Motorola, Inc.
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
280MHz to 450MHz Programmable ASK/FSK Transmitter MAX7060
ABSOLUTE MAXIMUM RATINGS
GPOVDD, VDD5 to GND.......................................-0.3V to +6.0V DVDD, PAVDD, and AVDD to GND .....................-0.3V to +4.0V ENABLE, SCLK_PWR0, SDI_PWR1, DIN, CS_DEV, LSHDN, FREQ0, FREQ1, FREQ2, GPO1, and GPO2_MOD to GND .....................-0.3V to (VDD5 + 0.3V) PAOUT, ROUT, and PAVOUT to GND ....................... -0.3V to (PAVDD + 0.3V) XTAL1 and XTAL2 to GND .................... -0.3V to (AVDD + 0.3V) Continuous Power Dissipation (TA = +70NC) 24-Pin Thin QFN (derate 14.7mW/NC above +70NC) ............................1167mW Operating Temperature Range ........................ -40NC to +125NC Storage Temperature Range............................ -60NC to +150NC Lead Temperature (soldering, 10s) ...............................+300NC Soldering Temperature (reflow) ......................................+260NC
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS (5V OPERATION)
(Typical Application Circuit, 50I system impedance, tuned for 315MHz to 434MHz operation. VDD5 = VGPOVDD = 4.5V to 5.5V, fRF = 280MHz to 450MHz, fXTAL = 15MHz to 16MHz, TA = -40NC to +125NC, unless otherwise noted. Typical values are at VDD5 = VGPOVDD = +5V, TA = +25NC, PA matched for optimum output power, unless otherwise noted. All min and max values are 100% tested at TA = +125NC and guaranteed by design and characterization over temperature, unless otherwise noted.) PARAMETER Supply Voltage Regulated Analog Supply Voltage SYMBOL VDD AVDD PLL on, PA off PLL on, PA on, data at 50% duty cycle (ASK), +10dBm (PApwr = 0x19) output power (Notes 1, 2) Active Supply Current IDD PLL on, PA on, data at 100% duty cycle, +10dBm (PApwr = 0x19) output power (Note 1) PLL on, PA on, data at 100% duty cycle, max (PApwr = 0x1E) output power (Note 1) Standby Current DIGITAL I/O Input High Threshold Input Low Threshold VIH VIL 0.9 x VDVDD 0.1 x VDVDD V V ISTDBY VENABLE < VIL, VLSHDN < VIL fRF = 315MHz fRF = 433.92MHz fRF = 315MHz CONDITIONS MIN 4.5 TYP 5 3.2 4.7 5.3 12.5 6.0 6.9 MAX 5.5 UNITS V V
fRF = 433.92MHz
14.2 mA
fRF = 315MHz fRF = 433.92MHz fRF = 315MHz fRF = 433.92MHz TA = +25NC TA = +85NC TA = +125NC
19 25 28 34 1.1 1.3 3.8
26 31.6
FA 6.1
2
______________________________________________________________________________________
280MHz to 450MHz Programmable ASK/FSK Transmitter
DC ELECTRICAL CHARACTERISTICS (5V OPERATION) (continued)
(Typical Application Circuit, 50I system impedance, tuned for 315MHz to 434MHz operation. VDD5 = VGPOVDD = 4.5V to 5.5V, fRF = 280MHz to 450MHz, fXTAL = 15MHz to 16MHz, TA = -40NC to +125NC, unless otherwise noted. Typical values are at VDD5 = VGPOVDD = +5V, TA = +25NC, PA matched for optimum output power, unless otherwise noted. All min and max values are 100% tested at TA = +125NC and guaranteed by design and characterization over temperature, unless otherwise noted.) PARAMETER Input Pulldown Sink Current Input Pullup Source Current SYMBOL IIH IIL ISINK = 100FA (GPO1 and GPO2_MOD, gp1bst bit = 0) ISINK = 200FA (GPO1), boost = on (gp1bst bit = 1) ISOURCE = 100FA (GPO1 and GPO2_MOD, gp1bst bit = 0) ISOURCE = 200FA (GPO1), boost = on (gp1bst bit = 1) CONDITIONS MIN TYP 6 5 VGPOVDD - 0.10 VGPOVDD - 0.14 0.10 V 0.14 MAX UNITS FA FA
MAX7060
Output-Voltage High
VOH
V
Output-Voltage Low
VOL
DC ELECTRICAL CHARACTERISTICS (3V OPERATION)
(Typical Application Circuit, 50I system impedance, tuned for 315MHz to 434MHz operation. VDD5 = VGPOVDD = VAVDD = VDVDD = VPAVDD = 2.1V to 3.6V, fRF = 280MHz to 450MHz, fXTAL = 15MHz to 16MHz, TA = -40NC to +125NC, unless otherwise noted. Typical values are at VDD5 = VGPOVDD = VAVDD = VDVDD = VPAVDD = 2.7V, TA = +25NC, PA matched for optimum output power, unless otherwise noted. All min and max values are 100% tested at TA = +125NC and guaranteed by design and characterization over temperature, unless otherwise noted.) PARAMETER Supply Voltage SYMBOL VDD PLL on, PA off fRF = 315MHz fRF = 433.92MHz CONDITIONS MIN 2.1 TYP 2.7 4.2 4.8 11 MAX 3.6 6.2 7.2 UNITS V
Active Supply Current
IDD
PLL on, PA on, data fRF = 315MHz at 50% duty cycle (ASK), +10dBm (PApwr = 0x19) output power fRF = 433.92MHz (Notes 1, 2) PLL on, PA on, data at 100% duty cycle, fRF = 315MHz +10dBm (PApwr = 0x19) output power f = 433.92MHz RF (Note 1)
13
mA
17.2 22 0.4 0.5 2.5 0.005 0.3 2.6
27 31.6
Standby Current
ISTDBY
VENABLE < VIL, VLSHDN < VIL VENABLE < VIL, VLSHDN > VIH
TA = +25NC TA = +85NC TA = +125NC TA = +25NC TA = +85NC TA = +125NC
FA 6.0 FA 6.0
Shutdown Current
ISHDN
_______________________________________________________________________________________
3
280MHz to 450MHz Programmable ASK/FSK Transmitter MAX7060
DC ELECTRICAL CHARACTERISTICS (3V OPERATION) (continued)
(Typical Application Circuit, 50I system impedance, tuned for 315MHz to 434MHz operation. VDD5 = VGPOVDD = VAVDD = VDVDD = VPAVDD = 2.1V to 3.6V, fRF = 280MHz to 450MHz, fXTAL = 15MHz to 16MHz, TA = -40NC to +125NC, unless otherwise noted. Typical values are at VDD5 = VGPOVDD = VAVDD = VDVDD = VPAVDD = 2.7V, TA = +25NC, PA matched for optimum output power, unless otherwise noted. All min and max values are 100% tested at TA = +125NC and guaranteed by design and characterization over temperature, unless otherwise noted.) PARAMETER DIGITAL I/O Input High Threshold Input Low Threshold Input Pulldown Sink Current Input Pullup Source Current VIH VIL IIH IIL ISINK = 100FA (GPO1 and GPO2_MOD, gp1bst bit = 0) ISINK = 200FA (GPO1) boost = on (gp1bst bit = 1) ISOURCE = 100FA (GPO1 and GPO2_MOD, gp1bst bit = 0) ISOURCE = 200FA (GPO1) boost = on (gp1bst bit = 1) 5 1.3 VGPOVDD - 0.10 VGPOVDD - 0.14 0.10 V 0.14 0.9 x VDVDD 0.1 x VDVDD V V FA FA SYMBOL CONDITIONS MIN TYP MAX UNITS
Output-Voltage High
VOH
V
Output-Voltage Low
VOL
AC ELECTRICAL CHARACTERISTICS (5V OPERATION)
(Typical Application Circuit, 50I system impedance, tuned for 315MHz to 434MHz operation, VDD5 = VGPOVDD = 4.5V to 5.5V, fRF = 280MHz to 450MHz, fXTAL = 15MHz to 16MHz, TA = -40NC to +125NC, unless otherwise noted. Typical values are at VDD5 = VGPOVDD = +5V, TA = +25NC, PA matched for optimum output power, unless otherwise noted. All min and max values are 100% tested at TA = +125NC and guaranteed by design and characterization over temperature, unless otherwise noted.) PARAMETER GENERAL CHARACTERISTICS Frequency Range ENABLE low-to-high transition, frequency settled to within 50kHz of the desired carrier (includes time for VPAVOUT to settle) ENABLE low-to-high transition, frequency settled to within 5kHz of the desired carrier (includes time for VPAVOUT to settle) ASK mode (no shaping) FSK mode Manchester encoded Nonreturn to zero Manchester encoded Nonreturn to zero 280 130 Fs 185 50 100 70 140 kbps 450 MHz SYMBOL CONDITIONS MIN TYP MAX UNITS
Power-On Time
tON
Maximum Data Rate (PApwr = 0x1E)
4
______________________________________________________________________________________
280MHz to 450MHz Programmable ASK/FSK Transmitter
AC ELECTRICAL CHARACTERISTICS (5V OPERATION) (continued)
(Typical Application Circuit, 50I system impedance, tuned for 315MHz to 434MHz operation, VDD5 = VGPOVDD = 4.5V to 5.5V, fRF = 280MHz to 450MHz, fXTAL = 15MHz to 16MHz, TA = -40NC to +125NC, unless otherwise noted. Typical values are at VDD5 = VGPOVDD = +5V, TA = +25NC, PA matched for optimum output power, unless otherwise noted. All min and max values are 100% tested at TA = +125NC and guaranteed by design and characterization over temperature, unless otherwise noted.) PARAMETER Carrier-Frequency Switching Time PLL VCO Gain KVCO fRF = 315MHz PLL Phase Noise fRF = 433.92MHz Loop Bandwidth Reference Frequency Input Level Frequency Divider Range Frequency Deviation (FSK) CRYSTAL OSCILLATOR Crystal Frequency Crystal Load Capacitance (Note 3) POWER AMPLIFIER Maximum output transmit power: PApwr = 0x1E Minimum output transmit power: PApwr = 0x00 +14.5 dBm -14 0.95 70 -24 -42 0 to 7.75 dB dB dBc dBc pF fXTAL 15 to 16 10 MHz pF 19 Q2 10kHz offset 1MHz offset 10kHz offset 1MHz offset 340 -78 -97 -74 -97 300 500 28 Q100 kHz kHz mVP-P dBc/Hz MHz/V SYMBOL CONDITIONS Time from end of SPI write or change of FREQ0, FREQ1, or FREQ2 pins, to frequency settled to within 5kHz of desired carrier MIN TYP MAX UNITS
MAX7060
60
Fs
Output Transmit Power (Note1)
POUT
Power-Control Step Size Modulation Depth (Note 1) Maximum Carrier Harmonics (Note 1) Reference Spur PAOUT Capacitor Tuning Range
_______________________________________________________________________________________
5
280MHz to 450MHz Programmable ASK/FSK Transmitter MAX7060
AC ELECTRICAL CHARACTERISTICS (3V OPERATION)
(Typical Application Circuit, 50I system impedance, tuned for 315MHz to 434MHz operation. VDD5 = VGPOVDD = VAVDD = VDVDD = VPAVDD = 2.1V to 3.6V, fRF = 280MHz to 450MHz, fXTAL = 15MHz to 16MHz, TA = -40NC to +125NC, unless otherwise noted. Typical values are at VDD5 = VGPOVDD = VAVDD = VDVDD = VPAVDD = 2.7V, TA = +25NC, PA matched for optimum output power, unless otherwise noted. All min and max values are 100% tested at TA = +125NC and guaranteed by design and characterization over temperature, unless otherwise noted.) PARAMETER GENERAL CHARACTERISTICS Frequency Range ENABLE low-to-high transition, frequency settled to within 50kHz of the desired carrier (includes time for VPAVOUT to settle) ENABLE low-to-high transition, frequency settled to within 5kHz of the desired carrier (includes time for VPAVOUT to settle) ASK mode (no shaping) FSK mode Manchester encoded Nonreturn to zero Manchester encoded Nonreturn to zero 280 120 Fs 200 50 100 70 140 kbps 450 MHz SYMBOL CONDITIONS MIN TYP MAX UNITS
Power-On Time
tON
Maximum Data Rate (PApwr = 0x19)
Carrier-Frequency Switching Time PLL VCO Gain KVCO
Time from end of SPI write or change of FREQ0, FREQ1, or FREQ2 pins, to frequency settled to within 5kHz of desired carrier
60
Fs
340 fRF = 315MHz 10kHz offset 1MHz offset 10kHz offset 1MHz offset -78 -97 -74 -97 300 500 19 Q2 28 Q100 15 to 16 4 10
MHz/V
PLL Phase Noise fRF = 433.92MHz Loop Bandwidth Reference Frequency Input Level Frequency Divider Range CRYSTAL OSCILLATOR Frequency Deviation (FSK) Crystal Frequency Frequency Pulling by Power Supply Crystal Load Capacitance (Note 3) POWER AMPLIFIER fXTAL
dBc/Hz
kHz mVP-P
kHz MHz ppm/V pF
VPAVDD = 2.1V, PApwr = 0x1E Output Transmit Power (Note1) Power-Control Step Size Modulation Depth (Note 1) 6 POUT VPAVDD = 3.6V, PApwr = 0x1E PApwr = 0x00
+10 +15 -14.5 0.95 70 dB dB dBm
______________________________________________________________________________________
280MHz to 450MHz Programmable ASK/FSK Transmitter
AC ELECTRICAL CHARACTERISTICS (3V OPERATION) (continued)
(Typical Application Circuit, 50I system impedance, tuned for 315MHz to 434MHz operation. VDD5 = VGPOVDD = VAVDD = VDVDD = VPAVDD = 2.1V to 3.6V, fRF = 280MHz to 450MHz, fXTAL = 15MHz to 16MHz, TA = -40NC to +125NC, unless otherwise noted. Typical values are at VDD5 = VGPOVDD = VAVDD = VDVDD = VPAVDD = 2.7V, TA = +25NC, PA matched for optimum output power, unless otherwise noted. All min and max values are 100% tested at TA = +125NC and guaranteed by design and characterization over temperature, unless otherwise noted.) PARAMETER Maximum Carrier Harmonics (Note 1) Reference Spur PAOUT Capacitor Tuning Range SYMBOL CONDITIONS MIN TYP -24 -43 0 to 7.75 MAX UNITS dBc dBc pF
MAX7060
SERIAL PERIPHERAL INTERFACE (SPI) TIMING CHARACTERISTICS
(SPI timing characteristics are valid for both 3V and 5V modes. SPI timing is production tested at worst-case temperature and supply with a clock frequency of 3MHz.) PARAMETER Minimum SCLK_PWR0 Low to Falling-Edge of CS_DEV Setup Time Minimum CS_DEV Low to Rising Edge of SCLK_PWR0 Setup Time Minimum SCLK_PWR0 Low to Rising Edge of CS_DEV Setup Time Minimum SCLK_PWR0 Low After Rising Edge of CS_DEV Hold Time Minimum Data Valid to SCLK_ PWR0 Rising-Edge Setup Time Minimum Data Valid to SCLK_ PWR0 Rising-Edge Hold Time Minimum SCLK_PWR0 High Pulse Width Minimum SCLK_PWR0 Low Pulse Width Minimum CS_DEV High Pulse Width Maximum Transition Time from Falling-Edge of CS_DEV to Valid GPO2_MOD Maximum Transition Time from Falling Edge of SCLK_PWR0 to Valid GPO2_MOD SYMBOL tSC tCSS tHCS tHS tDS CONDITIONS MIN TYP 30 15 60 15 30 MAX UNITS ns ns ns ns ns
tDH tCH tCL tCSH tCSG CL = 10pF load capacitance from GPO2_MOD to DGND CL = 10pF load capacitance from GPO2_MOD to DGND
15 120 120 120 400
ns ns ns ns ns
tCG
400
ns
Note 1: Supply current and output power are greatly dependent on board layout and PAOUT match. Note 2: 50% duty cycle at 10kHz ASK data (Manchester coded). Note 3: Dependent on PCB trace capacitance. _______________________________________________________________________________________ 7
280MHz to 450MHz Programmable ASK/FSK Transmitter MAX7060
CS_DEV tSC SCLK_PWRO tDS SDI_PWR1 tCSG GPO2_MOD tCG tDH tCSS tHCS tCL tCH tHS tCSH
Figure 1. SPI Timing Diagram
Typical Operating Characteristics
(Typical Application Circuit, 50I system impedance, VDD5 = VGPOVDD = VAVDD = VDVDD = VPAVDD = 2.1V to 3.6V, fRF = 280MHz to 450MHz, fXTAL = 16MHz, TA = -40NC to +125NC, unless otherwise noted. Typical values are at VDD5 = VGPOVDD = VAVDD = VDVDD = VPAVDD = 2.7V, TA = +25NC, PA matched for optimum output power, unless otherwise noted. Supply current and output power are greatly dependent on board layout and PAOUT match.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE (fRF = 315MHz, PA ON)
MAX7060 toc01
SUPPLY CURRENT vs. SUPPLY VOLTAGE (fRF = 315MHz, PA ON)
MAX7060 toc02
SUPPLY CURRENT vs. SUPPLY VOLTAGE (fRF = 315MHz, PA OFF)
3V MODE
7 SUPPLY CURRENT (mA) 6 5 4 3
MAX7060 toc03
30 28 26 SUPPLY CURRENT (mA) 24 22 20 18 16 14 12 10 2.1 2.4 2.7 3.0 3.3
30 28 26 SUPPLY CURRENT (mA) 24 22 20 18 16 14 12 10
8
3V MODE TA = +25C TA = -40C papwr = 0x1E TA = +125C TA = +85C +125C papwr = 0x16 -40C
5V MODE
papwr = 0x1E TA = -40C TA = +85C TA = +25C
TA = +125C TA = +85C
TA = +125C +125C papwr = 0x16
TA = +25C TA = -40C
-40C
2 4.5 4.7 4.9 5.1 5.3 5.5 2.1
3.6
2.4
2.7
3.0
3.3
3.6
VDD (V)
VDD (V)
VDD (V)
SUPPLY CURRENT vs. SUPPLY VOLTAGE (fRF = 433.92MHz, PA ON)
MAX7060 toc04
SUPPLY CURRENT vs. SUPPLY VOLTAGE (fRF = 433.92MHz, PA ON)
MAX7060 toc05
SUPPLY CURRENT vs. SUPPLY VOLTAGE (fRF = 433.92MHz, PA OFF)
3V MODE
7 SUPPLY CURRENT (mA) 6 5 4 3
MAX7060 toc06
38 36 34 SUPPLY CURRENT (mA) 32 30 28 26 24 22 20 18 16 14 2.1
36 34 32 SUPPLY CURRENT (mA) 30 28 26 24 22 20 18 16
3V MODE TA = +25C TA = -40C TA = +125C papwr = 0x1E TA = +85C -40C papwr = 0x16 +125C
2.4 2.7 3.0 3.3
papwr = 0x1E
5V MODE
8
TA = +125C TA = +85C
TA = +85C TA = +125C papwr = 0x16
TA = +25C
TA = -40C
-40C
TA = +25C TA = -40C
+125C
4.5 4.7 4.9 5.1 5.3 5.5 VDD (V)
2 2.1 2.4 2.7 3.0 3.3 3.6 VDD (V)
3.6
VDD (V)
8
______________________________________________________________________________________
280MHz to 450MHz Programmable ASK/FSK Transmitter
Typical Operating Characteristics (continued)
(Typical Application Circuit, 50I system impedance, VDD5 = VGPOVDD = VAVDD = VDVDD = VPAVDD = 2.1V to 3.6V, fRF = 280MHz to 450MHz, fXTAL = 16MHz, TA = -40NC to +125NC, unless otherwise noted. Typical values are at VDD5 = VGPOVDD = VAVDD = VDVDD = VPAVDD = 2.7V, TA = +25NC, PA matched for optimum output power, unless otherwise noted. Supply current and output power are greatly dependent on board layout and PAOUT match.)
OUTPUT POWER vs. SUPPLY VOLTAGE (fRF = 315MHz, PA ON)
MAX7060 toc07
MAX7060
OUTPUT POWER vs. SUPPLY VOLTAGE (fRF = 315MHz, PA ON)
MAX7060 toc08
OUTPUT POWER vs. SUPPLY VOLTAGE (fRF = 433.92MHz, PA ON)
3V MODE
14 12 POUT (dBm) 10 8 6 4
3V MODE
16 14 POUT (dBm) 12 10 8 6 4 2.1 2.4
TA = +25C T = +85C A TA = -40C
papwr = 0x1E
TA = +85C
5V MODE
15 13 POUT (dBm)
TA = +25C TA = +85C TA = -40C
papwr = 0x1E TA = +125C TA = +25C TA = -40C papwr = 0x16 TA = +85C
TA = -40C TA = +125C TA = +25C
papwr = 0x1E TA = +125C TA = -40C TA = +25C
11
TA = +85C
9 7
papwr = 0x16
TA = +25C
TA = +125C
TA = +125C
2.7 3.0 3.3 3.6
5 4.5
TA = -40C
4.7 4.9 5.1 5.3 5.5 VDD (V)
2 2.1
papwr = 0x16
2.4
TA = +85C
2.7 3.0
TA = +125C
3.3 3.6
VDD (V)
VDD (V)
OUTPUT POWER vs. SUPPLY VOLTAGE (fRF = 433.92MHz, PA ON)
MAX7060 toc10
PA POWER vs. PA POWER CODE, 315MHz
15 10
SUPPLY CURRENT vs. PA POWER CODE, 315MHz
MAX7060 toc11
papwr = 0x1E
TA = +85C
5V MODE
3V MODE
VDD = 3.6V
13 11 POUT (dBm)
30 SUPPLY CURRENT (mA) 25 20 15 10 5 0
3V MODE VDD = 3.6V
TA = +125C TA = +25C
9 7 5 3 4.5 4.7
TA = -40C
POUT (dBm)
5 0 -5 -10
VDD = 2.7V VDD = 2.1V
TA = -40C TA = +85C papwr = 0x16
VDD = 2.7V VDD = 2.1V
TA = +25C TA = +125C
4.9 5.1 5.3 5.5 VDD (V)
-15 0 5 10 15 20 25 30 35 PA POWER CODE (DECIMAL)
0
5
10
15
20
25
30
35
PA POWER CODE (DECIMAL)
PA POWER vs. PA POWER CODE, 315MHz
MAX7060 toc13
SUPPLY CURRENT vs. PA POWER CODE, 315MHz
MAX7060 toc14
PA POWER vs. PA POWER CODE, 433.92MHz
15 10 POUT (dBm) 5 0 -5 -10 VDD = 2.1V 3V MODE VDD = 3.6V VDD = 2.7V
MAX7060 toc15
16 12 8 POUT (dBm) 4 0 -4 -8 -12 -16 0
30
5V MODE
20
5V MODE
25 SUPPLY CURRENT (mA) 20 15
VDD = 4.5V
VDD = 5.5V
VDD = 4.5V
VDD = 5V
VDD = 5.5V
10
VDD = 5V
5
-15
25 30 35
5
10 15 20 25 30 PA POWER CODE (DECIMAL)
35
0
5
10
15
20
-20 0 5 10 15 20 25 30 PA POWER CODE (DECIMAL) 35
PA POWER CODE (DECIMAL)
_______________________________________________________________________________________
MAX7060 toc12
15
20
35
MAX7060 toc09
18
17
16
9
280MHz to 450MHz Programmable ASK/FSK Transmitter MAX7060
Typical Operating Characteristics (continued)
(Typical Application Circuit, 50I system impedance, VDD5 = VGPOVDD = VAVDD = VDVDD = VPAVDD = 2.1V to 3.6V, fRF = 280MHz to 450MHz, fXTAL = 16MHz, TA = -40NC to +125NC, unless otherwise noted. Typical values are at VDD5 = VGPOVDD = VAVDD = VDVDD = VPAVDD = 2.7V, TA = +25NC, PA matched for optimum output power, unless otherwise noted. Supply current and output power are greatly dependent on board layout and PAOUT match.)
SUPPLY CURRENT vs. PA POWER CODE, 433.92MHZ
MAX7060 toc16
PA POWER vs. PA POWER CODE, 433.92MHz
5V MODE
10 5
POUT (dBm)
SUPPLY CURRENT vs. PA POWER CODE, 433.92MHZ
MAX7060 toc17
40 SUPPLY CURRENT (mA) 35 30 25 20 15 10 5 0 0
3V MODE
VDD = 3.6V
VDD = 4.5V
5V MODE
30 SUPPLY CURRENT (mA) 25 20 15 10 5
VDD = 4.5V
VDD = 2.7V
0 -5
VDD = 5.5V VDD = 5V
VDD = 5.5V VDD = 5V
VDD = 2.1V
-10 -15 0 5 10
5
10
15
20
25
30
35
15
20
25
30
35
0
5
10
15
20
25
30
35
PA POWER CODE (DECIMAL)
PA POWER CODE (DECIMAL)
PA POWER CODE (DECIMAL)
PHASE NOISE vs. OFFSET FREQUENCY (fRF = 315MHz, TA = +25C, VDD = 2.7V, PA CODE = 0x19)
MAX7060 toc19
PHASE NOISE vs. OFFSET FREQUENCY (fRF = 433.92MHz, TA = +25C, VDD = 2.7V, PA CODE = 0x19)
MAX7060 toc20
REFERENCE SPUR MAGNITUDE vs. SUPPLY VOLTAGE
REFERENCE SPUR MAGNITUDE (dBc)
-70 PHASE NOISE (dBc/Hz) -80 -90 -100 -110 -120 -130 -140 1k 10k 100k 1M
-60 PHASE NOISE (dBc/Hz) -70 -80 -90 -100 -110 -120 -130
3V MODE
-42
433.92MHz 315MHz
-44
-46
-48 1k 10k 100k 1M 10M 2.1 2.4 2.7 3.0 3.3 3.6 OFFSET FREQUENCY (Hz) SUPPLY VOLTAGE (V)
10M
OFFSET FREQUENCY (Hz)
10
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MAX7060 toc21
-60
-50
-40
MAX7060 toc18
45
15
35
280MHz to 450MHz Programmable ASK/FSK Transmitter
Typical Operating Characteristics (continued)
(Typical Application Circuit, 50I system impedance, VDD5 = VGPOVDD = VAVDD = VDVDD = VPAVDD = 2.1V to 3.6V, fRF = 280MHz to 450MHz, fXTAL = 16MHz, TA = -40NC to +125NC, unless otherwise noted. Typical values are at VDD5 = VGPOVDD = VAVDD = VDVDD = VPAVDD = 2.7V, TA = +25NC, PA matched for optimum output power, unless otherwise noted. Supply current and output power are greatly dependent on board layout and PAOUT match.)
REFERENCE SPUR MAGNITUDE vs. SUPPLY VOLTAGE
MAX7060 toc22
MAX7060
FSK SPECTRUM (fRF = 315MHz, +25C, VDD = 2.7V, PA CODE = 0x19 50kHz DEVIATION, 4kHz SQUARE WAVE ON DIN)
RBW = 10kHz VBW = 10kHz
MAX7060 toc23
-40 REFERENCE SPUR MAGNITUDE (dBc)
20 10 POUT (dBm) 0 -10 -20 -30 314.5
5V MODE
-42
433.92MHz
-44
315MHz
-46
-48 4.5 4.7 4.9 5.1 5.3 5.5 SUPPLY VOLTAGE (V)
314.7
314.9
315.1
315.3
315.5
fRF (MHz)
Pin Configuration/Functional Diagram
AVDD PAVOUT 13
PULSE SHAPING
XTAL1
XTAL2
18
17
16
15
CRYSTAL OSCILLATOR CS_DEV 19
CHARGE PUMP
LOOP FILTER
VOLTAGE REGULATOR
VDD5 14
N.C.
12
ROUT
SDI_PWR1
20
PFD
VCO
PA POWER CONTROL
11
PAVDD
SCLK_PWR0
21
ENABLE
22
SERIAL INTERFACE, CONFIGURATION, AND CONTROL
FREQUENCY DIVIDER MODULATOR
PA 5
10
PAOUT
ASK DATA
9
N.C.
DIN
23 /K
MAX7060
3
EXPOSED PAD GND
8
LSHDN
N.C.
24
7
FREQ2
+
1 GPO2_MOD
2 GPO1
3 DVDD
4 GPOVDD
5 FREQ0
6 FREQ1
TQFN
______________________________________________________________________________________
11
280MHz to 450MHz Programmable ASK/FSK Transmitter MAX7060
Pin Description
PIN 1 2 3 4 5 6 7 8 9, 15, 24 10 11 12 13 14 16 17 18 19 20 21 22 23 -- NAME GPO2_MOD GPO1 DVDD GPOVDD FREQ0 FREQ1 FREQ2 LSHDN N.C. PAOUT PAVDD ROUT PAVOUT VDD5 AVDD XTAL2 XTAL1 CS_DEV SDI_PWR1 SCLK_PWR0 ENABLE DIN EP FUNCTION (SPI Mode/Manual Mode) Digital Input/Output. GPO2 output in SPI mode. Acts as an SPI data output when CS_DEV is low. ASK (0)/FSK (1) modulation select input in manual mode. This pin is internally pulled down in manual mode. General-Purpose Output 1. In SPI mode, this pin can output many internal status signals. In manual mode, this pin outputs the synthesizer lock-detect (lockdet) signal. Digital-Supply Voltage Input. Bypass to GND with a 0.01FF capacitor as close as possible to the pin. Power-Supply Voltage Input for GPOs and ESD-Protection Devices. Bypass to GND with a 0.01FF capacitor as close as possible to the pin. Frequency-Select Pin 0 in Manual Mode. Internally pulled down. FREQ0 = FREQ1 = FREQ2 = 0 for SPI mode. Frequency-Select Pin 1 in Manual Mode. Internally pulled down. FREQ0 = FREQ1 = FREQ2 = 0 for SPI mode. Frequency-Select Pin 2 in Manual Mode. Internally pulled down. FREQ0 = FREQ1 = FREQ2 = 0 for SPI mode. Low-Power Shutdown Current-Select Digital Input. Turns off internal POR circuit and disables pullup/pulldown currents. Must be driven low for normal operation in 3V mode. Functional only in 3V mode. Connect to GND in 5V mode. No Connection. Internally not connected. Leave unconnected. Power Amplifier Output. Requires a pullup inductor to PAVOUT, which can be part of the outputmatching network to an antenna. Power Amplifier Predriver Power-Supply Input. Bypass to GND with a 680pF capacitor and a 0.01FF as close as possible to the pin. Envelope-Shaping Resistor Connection. See the Typical Application Circuits and the ASK Envelope Shaping sections for details. Power Amplifier Power-Control Output. Controls the transmitted power. Connect to PA pullup inductor. Bypass to ground with 680pF capacitor. Supply Voltage Input. Bypass to ground with 0.01FF and 0.1FF capacitors. Analog Supply Voltage and Regulator Output. Bypass to GND with 0.1FF and 0.01FF capacitors as close as possible to the pin. Crystal Input 2. XTAL2 can be driven from an AC-coupled external reference. Crystal Input 1. AC-couple to GND if XTAL2 is driven from an AC-coupled external reference. (SPI Mode/Manual Mode) Serial Peripheral Interface (SPI) Active-Low Chip-Select Input. FSK frequency-deviation input (0 = low deviation, 1 = high deviation) in manual mode. Internally pulled up. (SPI Mode/Manual Mode) SPI Data Input in SPI Mode. Power-control MSB input in manual mode. Internally pulled down. (SPI Mode/Manual Mode) SPI Clock Input in SPI Mode. Power-control LSB input in manual mode. Internally pulled down. Enable Digital Input. All internal circuits (except the PA in ASK mode) are enabled on the rising edge of ENABLE. Internally pulled down. Transmit Data Digital Input. Internally pulled down. Exposed Pad. Solder evenly to the board's ground plane for proper operation.
12
_____________________________________________________________________________________
280MHz to 450MHz Programmable ASK/FSK Transmitter
Detailed Description
The MAX7060 is power and frequency programmable from 280MHz to 450MHz. The MAX7060 has an internal transmit power control that can be programmed over a 28dB power range. The MAX7060 has tuning capacitors at the output of the power amplifier (PA) to ensure highpower efficiency at various programmable frequencies with a single matching network. The crystal-based architecture of the MAX7060 eliminates many of the common problems with SAW transmitters by providing greater modulation depth, faster frequency settling, tighter tolerance of the transmit frequency, and reduced temperature dependence. In particular, the tighter transmit frequency tolerance means that a superheterodyne receiver with a narrower IF bandwidth (therefore lower noise bandwidth) can be used. The payoff is better overall receiver performance when using a superheterodyne receiver such as the MAX1473, MAX1471, MAX7033, MAX7034, MAX7036, and MAX7042. The MAX7060 can be configured in either SPI or manual mode, where the transmitter can easily be configured without the need of an SPI interface. In the 3V operation, the MAX7060 can be put in a lowpower shutdown mode by pulling ENABLE low and LSHDN high. In this mode, all the blocks are shut down including power-on reset (POR). All the MAX7060 registers must be reprogrammed after LSHDN is asserted high. In the 5V operation, the low-power shutdown mode is not available, and LSHDN should be connected to GND. The MAX7060 is a crystal-referenced phased-lockedloop (PLL) VHF/UHF transmitter that transmits data over a wide frequency range. The internal VCO can be tuned from 280MHz to 450MHz and controlled by a single crystal to cover up to a 1.47:1 carrier-frequency range. The transmit frequency is set by the crystal frequency and the programmable divider in the PLL; the programmable PLL divide ratios can be set anywhere from 19 to 28, which means that with a crystal frequency of 15MHz, the output is 285MHz to 420MHz. With a crystal frequency of 16MHz, the output is 304MHz to 448MHz. The MAX7060 has an internal variable capacitor connected across the PA output. This capacitor can be programmed to maintain high-efficiency transmission at any frequency within a 1.47 to 1 (28/19) tuning range. This means that it is possible to change the frequency and retune the antenna to the new frequency in a very short time. The combination of rapid antenna-tuning ability with rapid synthesizer tuning makes the MAX7060 a true frequency-agile transmitter. The tuning capacitor has a nominal resolution of 0.25pF, from 0 to 7.75pF. The MAX7060 supports data rates up to 100kbps NRZ in ASK mode and 140kbps NRZ in FSK mode. In FSK mode, the frequency deviation corresponding to bit 1 and bit 0 can be set as low as Q2kHz, and as high as Q100kHz. The frequency deviation is fully programmable in SPI mode, and can be selected either as Q16kHz or Q50kHz in manual mode. The PA of the MAX7060 is a high-efficiency, open-drain switching-mode amplifier. In a switching-mode amplifier, the gate of the final-stage FET is driven with a very sharp 25% duty-cycle square wave at the transmit frequency. This square wave is derived from the synthesizer circuit. When the matching network is tuned correctly, the output FET resonates the attached tank circuit with a minimum amount of power dissipated in the FET. With a proper output-matching network, the PA can drive a wide range of antenna impedances, which include a small-loop PCB trace and a 50I antenna. The output-matching network suppresses the carrier harmonics and transforms the antenna impedance to an optimal impedance at PAOUT, which is from 60I to 125I. When the output-matching network is properly tuned, the MAX7060 transmits power with a high overall efficiency. The efficiency of the PA itself is approximately 50%. The transmitter power of the MAX7060 can be set in approximately 1dB steps (SPI mode) to produce a maximum output power level of +14dBm with a 5V supply. If a battery is used as the supply, the maximum output power level varies from +15dBm at 3.6V to +10dBm at 2.1V. The minimum power level is -14dBm for both 5V and battery supplies. The maximum transmitter power (and the transmitter current) can be lowered by increasing the load impedance on the PA. Four fixed power levels are available in manual mode. When a 5V supply is used, the VDD5 and GPOVDD pins are connected to the 5V supply. AVDD is the output of an internal voltage regulator and must be connected externally to DVDD and PAVDD. The PAVOUT pin is connected to the PAOUT pin through a biasing inductor. PAVOUT is not connected to any of the power-supply
MAX7060
Power Amplifier (PA)
Frequency Programming
Transmitter Power Control
______________________________________________________________________________________
13
280MHz to 450MHz Programmable ASK/FSK Transmitter MAX7060
pins. Connecting PAVOUT to PAOUT enables Tx power control. In SPI mode, there are 31 power-control settings in approximately 1dB monotonic steps. In manual mode, four power-control settings are available. The MAX7060 has two types of ASK envelope shaping: digital shaping (SPI mode only) and analog shaping through an internal resistor. Envelope shaping results in a smaller spectral width of the modulated PA output signal. The fractional-N architecture also allows exact FSK frequency deviations to be programmed, completely eliminating the problems associated with generating frequency deviations by crystal oscillator pulling. FSK deviations as low as Q2kHz and as high as Q100kHz can be set in SPI mode. In manual mode, the user can select between Q16kHz and Q50kHz. The integer and fractional portions of the PLL divider ratio set the transmit frequency. This is done by loading the divide-ratio registers in SPI mode, or selecting the states of the three frequency-control pins (FREQ2, FREQ1, FREQ0) in manual mode. For ASK modulation, the two 8-bit center-frequency registers (fce[15:0]) are loaded with the divide ratio determined by the center frequency and the crystal. For FSK modulation, the two 8-bit high (mark) frequency registers (fhi[15:0]) and the two 8-bit low (space) frequency registers (flo[15:0]) are loaded. The divide ratios for the fhi and flo are determined by the center frequency, the frequency deviation, and the crystal frequency. Examples of typical settings for ASK and FSK modulation are given in the SPI Mode Settings section. The XTAL oscillator in the MAX7060 is designed to present a capacitance of approximately 6pF between the XTAL1 and XTAL2 pins. In most cases, this corresponds to a 8pF load capacitance applied to the external crystal when typical PCB parasitics are added. It is very important to use a crystal with a load capacitance equal to the capacitance of the MAX7060 crystal oscillator plus PCB parasitics. If a crystal designed to oscillate with a different load capacitance is used, the crystal is pulled away from its stated operating frequency, introducing an error in the reference frequency. A crystal designed to operate at a higher load capacitance than the value specified for the oscillator is always pulled higher in frequency. Adding capacitance to increase the load capacitance on the crystal increases the startup time and can prevent oscillation altogether. In actuality, the oscillator pulls every crystal. The crystal's natural frequency is really below its specified frequency, but when loaded with the specified load capacitance, the crystal is pulled and oscillates at its specified frequency. This pulling is already accounted for in the specification of the load capacitance.
ASK Envelope Shaping
In digital shaping, the user can choose the final Tx power setting, the power step size in units as small as 1dB, and the step-time interval in units as small as 0.25Fs, when a 16MHz crystal is used. This shaping method causes the PA to transmit an envelope that rises linearly in decibels (exponentially in power) with time. Digital shaping is programmed through the SPI. The analog shaping mode uses an internal envelopeshaping resistor for ASK modulation, which connects between PAVOUT and ROUT. When connected to the PA pullup inductor, the envelope-shaping resistor slows the turn-on/turn-off time of the PA. The user can choose three turn-on/turn-off times through the SPI. A single turnon/turn-off time is set internally in manual mode. The MAX7060 has an internal set of capacitors that can be switched in and out to present different capacitor values at the PA output. The capacitors are connected from the PA output to ground. This allows changing the tuning network along with the synthesizer divide ratio each time the transmitted frequency changes, making it possible to maintain maximum transmitter power while moving rapidly from one frequency to another. In SPI mode, the variable capacitor is programmed through a register setting. In manual mode, the capacitor setting is programmed through the DIN pin. The tuning capacitor has a nominal resolution of 0.25pF, from 0 to 7.75pF. The MAX7060 utilizes a fully integrated fractional-N PLL for its frequency synthesizer. All PLL components, including the loop filter, are included on-chip. Two loop bandwidths can be selected in SPI mode. The synthesizer has 16-bit fractional-N topology (4 bits integer, 12 bits fractional) with a divide ratio that can be set from 19 to 28, allowing the transmit frequency to be adjusted in increments of fXTAL/4096.
Crystal (XTAL) Oscillator
Variable Capacitor
Phase-Locked Loop (PLL)
14
_____________________________________________________________________________________
280MHz to 450MHz Programmable ASK/FSK Transmitter
Additional pulling can be calculated if the electrical parameters of the crystal are known. The frequency pulling is given by: fP = where: fP is the amount the crystal frequency pulled in ppm CM is the motional capacitance of the crystal CCASE is the case capacitance CSPEC is the specified load capacitance CLOAD is the actual load capacitance When the crystal is loaded as specified (i.e., CLOAD = CSPEC), the frequency pulling equals zero. CM 1 1 6 - x 10 2 C CASE + C LOAD C CASE + C SPEC The GPO2_MOD pin acts as the SPI data output when the CS_DEV pin is low, in SPI mode. When CS_DEV is high, it acts as a GPO that can output various internal signals, such as the synthesizer lock detect (lockdet). In SPI mode, the output clock that can be routed through GPO1 is a divided version of the crystal frequency. The divide ratio is set through the MAX7060 registers, and the divide settings are 1 (no division), 2, 4, 8, or 16. An external buffer is recommended to drive external devices if divide settings of 1, 2, and 4 are selected. The MAX7060 utilizes a 4-wire SPI protocol for programming its registers, configuring and controlling the operation of the whole transmitter. For SPI operation, the FREQ2, FREQ1, and FREQ0 pins must be reset to 0. The following digital I/Os control the operation of the SPI: CS_DEV SDI_PWR1 SCLK_PWR0 GPO2_MOD Active-low SPI chip select SPI data Input SPI clock SPI data output
MAX7060
Serial Peripheral Interface (SPI)
The MAX7060 has two GPO pins in SPI mode (GPO2_ MOD and GPO1) and one GPO in manual mode (GPO1).
General-Purpose Output (GPO)/Clock Outputs
The GPO1 pin can serve as a clock for a microprocessor or any other GPO function in SPI mode. In manual mode, this pin outputs the synthesizer lock-detect (lockdet) status, after which the user can send data through the DIN pin.
Figure 2 shows the general timing diagram of the SPI protocol. Any number of 8-bit data bursts (Data 1, Data 2 ... Data n) can be sent within one cycle of the CS_DEV pin, to allow for burst-write or burst-read operations. The SPI data output signal is routed through the GPO2_MOD pin when CS_DEV is low.
CS_DEV
SCLK_PWR0
SDI_PWR1
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
GPO2_MOD
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
DATA 1
DATA n
Figure 2. SPI Format
______________________________________________________________________________________
15
280MHz to 450MHz Programmable ASK/FSK Transmitter MAX7060
The following commands are implemented in the MAX7060: Write: Within the same CS_DEV cycle, a write command is implemented as follows: SDI_PWR1: <0x01> ... With this command, Data 1 is written to the address given by , Data 2 is written to , and so on. Read: Within the same CS_DEV cycle, a read command is implemented as follows: SDI/PWR1: GPO2_MOD: <0x02>

<0xXX> <0xXX>

...

... <0x00>
SPI Commands
With this command, all the registers can be read within the same cycle of CS_DEV. The addresses can be given in any order.
CS_DEV
SCLK_PWR0
SDI_PWR1 WRITE COMMAND (0x01)
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2 D1
D0
D7 DATA N
D0
INITIAL ADDRESS (A[7:0])
DATA 1
Figure 3. SPI Write Command Format
CS_DEV
SCLK_PWR0 SDI_PWR1 READ COMMAND (0x02) GPO2_MOD A7 A6 A5 A4 A3 A2 A1 A0 A7 A6 A5 A4 A3 A2 A1 A0 A7 A0
0x00
ADDRESS 1
ADDRESS 2
ADDRESS N
D7 D6 D5 D4 D3 D2 D1 D0 D7 DATA 1 DATA 2
D0 D7 DATA N
D0
Figure 4. SPI Read Command Format
16
_____________________________________________________________________________________
280MHz to 450MHz Programmable ASK/FSK Transmitter
Read All: Within two CS_DEV cycles, the read-all command is implemented as follows: CS_DEV Cycle 1 SDI_PWR1: GPO2_MOD: SDI_PWR1: <0x04> <0x03>

<0x00> CS_DEV Cycle 2 <0x00> <0x00> ... <0x00> ...
MAX7060
Reset: An SPI reset command is implemented as follows: An internal active-low master reset pulse is generated, from the falling edge of the last SCLK_PWR0 signal to the falling edge of the following CS_DEV signal (tHCS + tCSH).
CS_DEV SCLK_PWR0
SDI_PWR1 READ-ALL COMMAND (0x03) GPO2_MOD
A7 A6 A5 A4 A3 A2 A1 A0 ADDRESS N D7 D6 D5 D4 D3 D2 D1 D0 D7 DATA N D0 D7 D0
DATA N + 1
DATA N + n
Figure 5. SPI Read-All Command Format
CS_DEV
SCLK_PWRO
SDI_PWR1 RESET COMMAND (0x04) INTERNAL RESET PULSE
Figure 6. SPI Reset Command Format
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17
280MHz to 450MHz Programmable ASK/FSK Transmitter MAX7060
Applications Information
SPI Mode Settings ASK Carrier Frequency
The output power level is set by entering a 5-bit value into the PApwr register (papwr[4:0]). The highest setting (30dec or 0x1E) corresponds to the highest transmitted power level. Each step is slightly less than 1dB (approximately 0.95dB), with the lowest setting producing a transmitted power 28dB lower than the highest. The highest transmitted power depends on the load presented to the PA output. A 50I or 60I load produces an output power level of +14dBm to +15dBm when the highest papwr[4:0] setting (0x1E) is applied. Increasing the load resistance reduces the output power level. Reducing the setting by one step reduces the power by approximately 1dB, and the minimum transmitted power is still about 28dB below the maximum. For example, if the load resistance is increased to the point where the output power for the maximum setting (0x1E) is +10dBm, then the minimum setting (0x00) produces an output power of about -18dBm. The output power level in 3V operation is set the same way as in 5V operation, but the variation in the 3V supply (the specified range is 2.1V to 3.6V) affects the maximum power that can be transmitted. If the supply is 3.6V, then the maximum papwr[4:0] setting (0x1E) still produces a +14dBm to +15dBm transmitted power level. As the supply voltage decreases, the transmitted power at the highest settings is compressed, so that the top setting and an increasing number of the lower settings produce the same transmitted power, which is lower than the +14dBm to +15dBm achieved with a 3.6V supply. For example, a 2.7V supply produces a maximum transmitter power of +12dBm to +13dBm, and the PApwr register settings from 0x1B to 0x1E (27dec to 30dec) produce the same transmitter power. Below this compressed range, the power settings give the same power levels that they would give with a 5V supply. At the lowest supply level of 2.1V, the maximum setting produces a maximum transmitter power of +10dBm, and the PApwr register settings from 0x19 to 0x1E (25dec to 30dec) produce the same transmitter power. The effect of a lower supply voltage reduces the maximum power and the adjustment range. The power at the lowest setting remains unchanged. The transmitted power using a 3V supply can be set higher than the levels described in the paragraph above by connecting PAOUT directly to PAVDD and disconnecting (leave open) the PAVOUT pin. The tradeoff of this connection is that there is no transmit power adjustment.
Transmit Power Settings (5V Supply)
When the MAX7060 is in ASK mode, only the carrier frequency needs to be set. To do this, the user calculates the divide ratio based on the carrier frequency and crystal frequency. The example below shows how to determine the correct value to be loaded into the carrierfrequency registers (fce[15:0]). Due to the nature of the transmit PLL frequency divider, a fixed offset of 16 must be subtracted from the transmit PLL divider ratio for programming the MAX7060's transmit-frequency registers. To determine the value to program the MAX7060's transmit-frequency registers, convert the decimal value of the following equation to the nearest hexadecimal value: fRF decimal value to program the - 16 x 4096 = transmit-frequency registers fXTAL Assume the ASK transmit frequency = 315MHz and fXTAL = 16MHz. In this example, the rounded decimal value is 15,104 or 0x3B00. The upper byte (0x3B) is loaded into the FCenter0 register (fce[15:8]) and the lower byte (0x00) is loaded into the FCenter1 register (fce[7:0]). When the MAX7060 is in FSK mode, two frequencies need to be set: the mark (logical 1) frequency and the space (logical 0) frequency. In most cases, the two frequencies are above and below the carrier frequency by the deviation frequency. Therefore, the user needs to calculate the divide ratio for both frequencies and load them into four registers. The procedure for calculating the register settings is the same as it is for calculating the carrier frequency. The example below shows how to determine the register settings for the mark and space frequencies when the frequency deviation is 50kHz (100kHz between mark and space). Assume that, for an FSK transmitter centered at 433.92MHz, the mark frequency is 433.97MHz, the space frequency is 433.87MHz, and the crystal frequency is 16MHz. In this example, the rounded decimal value for the mark frequency is 45,560 or 0xB1F8. For the space frequency, the rounded decimal value is 45,535 or 0xB1DE. The mark setting is loaded into the FHigh0 and FHigh1 registers (fhi[15:0]), and the space setting is loaded into the FLow0 and FLow1 registers (flo[15:0]).
Transmit Power Settings (3V Supply)
FSK Mark and Space Frequencies
18
_____________________________________________________________________________________
280MHz to 450MHz Programmable ASK/FSK Transmitter
At data rates higher than 30kbps Manchester (60kbps NRZ), it may be necessary to shape the ASK transmitter pulses to reduce the occupied bandwidth of the transmitted signal to comply with government regulations (FCC in the U.S., ETSI in Europe). There is no shaping of the FSK modulation. The MAX7060 has two forms of amplitude shaping: digital and analog. The digital shaping feature allows the user to choose a linear stairstep function to increase and decrease the power when the PA is turned on and off for an ASK bit interval. There are three registers that control the digital amplitude shaping settings. The first setting is the final power of the PA when the pulse reaches its maximum (PApwr register). The second setting is the amplitude change, in decibels, for each step, which is the vertical axis of the stairstep (PAstep register). The third setting is the time interval of each step, which is the horizontal axis of the stairstep (Tstep register). The final power setting (decimal 0 to 30 in increments of 1dB) is entered in the PApwr register. The amplitude step (decimal 0 to 30 in increments of 1dB) is entered in the PAstep register. The time interval (decimal 0 to 60/fXTAL in increments of 4/fXTAL) is entered in the Tstep register. For example, to shape an 80kbps NRZ data stream (12.5Fs bit interval), the user might choose a maximum power level of 0x1E (30dec), an amplitude step of 5dB, and a time interval of 0.5Fs assuming a crystal frequency of 16MHz. This would produce an ASK pulse that ramps up in 3Fs, levels off for 9.5Fs, and ramps down in 3Fs. Because the amplitude steps are in decibels, the shape of the pulse
ASK Amplitude Shaping
rise and fall is exponential on a linear display (an oscilloscope, for instance). Because most ASK receivers use a logarithmic amplitude detector, the demodulated pulse has a linear ramp shape. The digital shaping is disabled when the Tstep register is 0x00. To use the analog shaping feature, the user must connect the bias inductor to the ROUT pin instead of directly to the PAVOUT pin. This places a MOS resistor between PAVOUT and PAOUT, which slows down the application of the PAVOUT voltage to the drain of the PA FET when the PA is turned on. There are three settings in the anshp[1:0] bits in the Conf0 register for the rate at which the pulse ramps up: anshp[1:0] = 11 is the fastest (approximately 1Fs); anshp[1:0] = 10 is approximately 1.5Fs and anshp[1:0] = 01 is approximately 3Fs; and anshp[1:0] = 00 setting opens the connection between PAOUT and PAVOUT, disabling the analog amplitude shaping feature. The internal variable shunt capacitor, which can be used to match the PA to the antenna with changing transmitter frequency, is controlled by setting the 5-bit cap variable in the registers. This allows for 32 levels of shunt capacitance control. Since the control of these 5 bits is independent of the other settings, any capacitance value can be chosen at any frequency, making it possible to maintain maximum transmitter efficiency while moving rapidly from one frequency to another. The internal tuning capacitor adds 0 to 7.75pF to the PA output in 0.25pF steps. The PA output capacitance at the minimum cap setting is approximately 4.5pF.
MAX7060
Analog Amplitude Shaping
Digital Amplitude Shaping
Tuning Capacitor Settings
12.5s DIN PApwr = 0x1E (30dec) 0
12.5s
PAstep = 0x05 (5dB)
PAstep = 0x05 (5dB)
Tstep = 0x2 (0.5s)
Tstep = 0x2 (0.5s)
Figure 7. Digital Amplitude Shaping Timing Diagram ______________________________________________________________________________________ 19
280MHz to 450MHz Programmable ASK/FSK Transmitter MAX7060
Register Details
The following tables provide information on the MAX7060 registers.
Table 1. Register Summary
REGISTER Ident Conf0 Conf1 Conf2 IOConf0 IOConf1 Tstep PAstep PApwr FHigh0 FHigh1 FCenter0 FCenter1 FLow0 FLow1 FLoad EnableReg DataReg Status ADDRESS 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 DESCRIPTION Read-only register used for identification purpose. The content of this register is always 0xA6. Configuration 0 register. Controls the GPO1 boost mode, PLL bandwidth, analog shaping, crystal clock output, and the modulation mode (ASK/FSK). Configuration 1 register. Controls the clock output frequency divider and the capacitance at the PA output. Configuration 2 register. Controls the emulation mode. IO configuration 0 register. Selects the status register bus for SPI operation. IO configuration 1 register. Selects the outputs of GPO1 and GPO2_MOD pins. Digital shaping time step register. Controls the time step in the digital shaping. Digital shaping power step register. Controls the power step in the digital shaping. Final power register. Controls the final output power. High-frequency 0 register (upper byte). Sets the high frequency in FSK transmission. High-frequency 1 register (lower byte). Sets the high frequency in FSK transmission. Center-frequency 0 register (upper byte). Sets the carrier frequency in ASK transmission. Center-frequency 1 register (lower byte). Sets the carrier frequency in ASK transmission. Low-frequency 0 register (upper byte). Sets the low frequency in FSK transmission. Low-frequency 1 register (lower byte). Sets the low frequency in FSK transmission. Frequency-load register. Performs the frequency-load function. Enable register. Register equivalent of ENABLE pin. Datain register. Register equivalent of DIN pin. Status register
Table 2. Configuration Registers
REGISTER Ident Conf0 Conf1 Conf2 IOConf0 IOConf1 Tstep PAstep PApwr FHigh0 FHigh1 FCenter0 FCenter1 ADDRESS 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C DATA BIT 7 1 -- ckdiv_2 fixed -- -- -- -- -- fhi_15 fhi_7 fce_15 fce_7 BIT 6 0 gp1bst ckdiv_1 fxmode -- gp2s_2 -- -- -- fhi_14 fhi_6 fce_14 fce_6 BIT 5 1 pllbw ckdiv_0 fxpwr_1 -- gp2s_1 -- -- -- fhi_13 fhi_5 fce_13 fce_5 BIT 4 0 anshp_1 cap_4 fxpwr_0 -- gp2s_0 -- pastp_4 papwr_4 fhi_12 fhi_4 fce_12 fce_4 BIT 3 0 anshp_0 cap_3 fxhdev -- -- tstep_3 pastp_3 papwr_3 fhi_11 fhi_3 fce_11 fce_3 BIT 2 1 clksby cap_2 fxfrq_2 tmux_2 gp1s_2 tstep_2 pastp_2 papwr_2 fhi_10 fhi_2 fce_10 fce_2 BIT 1 1 clkout cap_1 fxfrq_1 tmux_1 gp1s_1 tstep_1 pastp_1 papwr_1 fhi_9 fhi_1 fce_9 fce_1 BIT 0 0 mode cap_0 fxfrq_0 tmux_0 gp1s_0 tstep_0 pastp_0 papwr_0 fhi_8 fhi_0 fce_8 fce_0 MODE R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
20
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280MHz to 450MHz Programmable ASK/FSK Transmitter
Table 2. Configuration Registers (continued)
REGISTER FLow0 FLow1 FLoad EnableReg DataReg Status ADDRESS 0x0D 0x0E 0x0F 0x10 0x11 0x12 DATA BIT 7 flo_15 flo_7 -- -- -- status_7 BIT 6 flo_14 flo_6 -- -- -- status_6 BIT 5 flo_13 flo_5 -- -- -- status_5 BIT 4 flo_12 flo_4 -- -- -- status_4 BIT 3 flo_11 flo_3 -- -- -- status_3 BIT 2 flo_10 flo_2 -- -- -- status_2 BIT 1 flo_9 flo_1 -- -- -- status_1 BIT 0 flo_8 flo_0 hop enable datain status_0 MODE R/W R/W R/W R/W R/W R
MAX7060
Table 3. Identification (Ident) Register (Address: 0x00)
BIT 7:0 NAME ident FUNCTION Read-only register used for identification purpose. The content of this register is always 0xA6.
Table 4. Configuration 0 (Conf0) Register (Address: 0x01)
BIT 6 5 NAME gp1bst pllbw 0 = Normal GPO1 output driver 1 = Extended driving capability on GPO1 PLL bandwidth setting, low (0) = 300kHz or high (1) = 600kHz; 300kHz is recommended for fractional-N and 600kHz for fixed-N (ASK mode only) Control time constants of the analog shaping anshp[1:0] Rise/fall time 00 no analog shaping 01 nominal 3.0Fs rise/fall time 10 nominal 1.5Fs rise/fall time 11 nominal 1.0Fs rise/fall time Crystal clock output enable (1) while part is in standby mode Crystal clock output enable (1) on GPO1 output, gp1s[2:0] = 0x2 ASK (0) or FSK (1) FUNCTION
4:3
anshp[1:0]
2 1 0
clksby clkout mode
Table 5. Configuration 1 (Conf1) Register (Address: 0x02)
BIT 7:5 4:0 NAME ckdiv[2:0] cap[4:0] FUNCTION 3-bit clock output frequency divider 5-bit capacitor setting
Table 6. Crystal Divide Settings for Clock Output
ckdiv[2:0] 000 001 010 011 1XX CRYSTAL FREQUENCY DIVIDED BY 1 2 4 8 16
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280MHz to 450MHz Programmable ASK/FSK Transmitter MAX7060
Table 7. Configuration 2 (Conf2) Register (Address: 0x03)
BIT 7 6 NAME fixed fxmode Enable (1) or disable (0) emulation mode FSK (1) or ASK (0) Output power setting fxpwr[1:0] dB below PMAX 00 0 01 3 10 6 11 10 100kHz (1) or 32kHz (0) frequency deviation in FSK Frequency selection The combinations are same as those in manual mode. When a 16MHz crystal is used, the following frequency values are selected by fxfrq[2:0]. fxfrq[2:0] Freq (MHz) Divide Ratio 000 N/A N/A 001 315.00 19.68750 010 433.62 27.10125 011 390.00 24.37500 100 418.00 26.12500 101 372.00 23.25000 110 345.00 21.56250 111 433.92 27.12000 FUNCTION
5:4
fxpwr[1:0]
3
fxhdev
2:0
fxfrq[2:0]
Table 8. IO Configuration 0 (IOConf0) Register (Address: 0x04)
BIT 2:0 NAME tmux[2:0] Status register output selection bits FUNCTION
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280MHz to 450MHz Programmable ASK/FSK Transmitter
Table 9. IO Configuration 1 (IOConf1) Register (Address: 0x05)
BIT NAME GPO2 output selection CS_DEV Bit 2 0 X 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 GPO1 output selection Bit 2 Bit 1 Bit 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Bit 1 X 0 0 1 1 0 0 1 1 Bit 0 X 0 1 0 1 0 1 0 1 FUNCTION GPO2_MOD SPI Data Output lockdet -- ckout -- -- nock -- --
MAX7060
6:4
gp2s[2:0]
2:0
gp1s[2:0]
GPO1 lockdet -- ckout -- -- nock -- --
where: -- nock ckout Reserved signals No-clock flag (1) if crystal oscillator is disabled, and (0) if clock activity is observed Clock output signal, according to programmed dividers (ckdiv[2:0])
lockdet PLL lock-detect flag
Table 10. ASK Digital Shaping Time Step (Tstep) Register (Address: 0x06)
BIT 3:0 NAME tstep[3:0] FUNCTION Time interval value used in digital shaping, in increments of 4/fXTAL
Table 11. PA Digital Shaping Amplitude Step (PAStep) Register (Address: 0x07)
BIT 4:0 NAME pastp[4:0] FUNCTION Power step in digital shaping, in increments of 1dB
Table 12. PA Power (Papwr) Register (Address: 0x08)
BIT 4:0 NAME papwr[4:0] Final PA output power setting FUNCTION
Table 13. FSK High-Frequency 0 (FHigh0) Register (Address: 0x09)
BIT 7:0 NAME fhi[15:8] FUNCTION 8-bit upper byte of high-frequency divider for FSK 23
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280MHz to 450MHz Programmable ASK/FSK Transmitter MAX7060
Table 14. FSK High-Frequency 1 (FHigh1) Register (Address: 0x0A)
BIT 7:0 NAME fhi[7:0] FUNCTION 8-bit lower byte of high-frequency divider for FSK
The 4 MSBs of FHigh0, fhi[15:12], are the integer portion of the divider, excluding offset of 16. The 12 LSBs (fhi[11:0]) are the fractional part of the divider.
Table 15. ASK Center-Frequency 0 (FCenter0) Register (Address: 0x0B)
BIT 7:0 NAME fce[15:8] 8-bit upper byte of frequency divider for ASK FUNCTION
Table 16. ASK Center-Frequency 1 (FCenter1) Register (Address: 0x0C)
BIT 7:0 NAME fce[7:0] 8-bit lower byte of frequency divider for ASK FUNCTION
The 4 MSBs of Fcenter0, fce[15:12], are the integer portion of the divider, excluding offset of 16. The 12LSBs (fce[11:0) are the fractional part of the divider. When fce[11:0] are all zeros and ASK mode is selected (mode bit = 0), the PLL works in the fixed-N mode, which reduces current consumption and reference spurs. Set pllbw bit high (CONF0 register, bit 5). For all other combinations, the PLL works in fractional-N mode.
Table 17. FSK Low-Frequency 0 (FLow0) Register (Address:0x0D)
BIT 7:0 NAME flo[15:8] FUNCTION 8-bit upper byte of low-frequency divider for FSK
Table 18. FSK Low-Frequency 1 (FLow1) Register (Address: 0x0E)
BIT 7:0 NAME flo[7:0] FUNCTION 8-bit lower byte of low-frequency divider for FSK
The 4 MSBs of FLow0, flo[15:12], are the integer portion of the divider, excluding offset of 16. The 12 LSBs (flo[11:0]) are the fractional part of the divider.
Table 19. Maximum and Minimum Values for Frequency Divider
DECIMAL VALUE 12.0220 2.9536 fhi[15:0], fce[15:0], flo[15:0] 0xC05A 0x2F42
Table 20. Frequency-Load (FLoad) Register (Address: 0x0F)
BIT 0 NAME hop FUNCTION Effectively changes the PLL frequency to the ones written in registers 0x09 to 0x0E. This is a self-reset bit and is reset to zero after the operation is completed.
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280MHz to 450MHz Programmable ASK/FSK Transmitter
Table 21. Enable (EnableReg) Register (Address: 0x10)
BIT 0 NAME enable FUNCTION SPI equivalent of the ENABLE pin, which should be kept low (0) if the external ENABLE pin is used. The external ENABLE pin should also be kept low (0) if the enable bit is used.
MAX7060
Table 22. Data Input (DataReg) Register (Address: 0x11)
BIT 0 NAME datain FUNCTION SPI equivalent of DIN, where the transmitted data can be controlled through the SPI interface. It should be kept low (0) if only the external DIN pin is used. The external DIN pin should also be kept low (0) if the datain bit is used.
Table 23. Status (Status) Register (Address: 0x12)
BIT 7:0 NAME status[7:0] FUNCTION Read-only status register, selected through tmux[2:0] (register 0x04 IOConf0)
Table 24. Status Bus Signals
tmux[2:0] 0 1 2 3 4 5 6 7 status[7] -- -- -- -- -- integ[3] frac[7] -- status[6] -- -- -- frac_fxdb -- integ[2] frac[6] -- status[5] -- -- -- -- notover integ[1] frac[5] -- status[4] -- -- -- cap[4] capfxd[4] integ[0] frac[4] -- status[3] ckout -- enable cap[3] capfxd[3] frac[11] frac[3] -- status[2] ckd16 -- -- cap[2] capfxd[2] frac[10] frac[2] -- status[1] ckd4 -- -- cap[1] capfxd[1] frac[9] frac[1] lockdet status[0] nock -- -- cap[0] capfxd[0] frac[8] frac[0] xmit_en
-- nock ckd4 ckd16 ckout enable cap[4:0]
Reserved signals No-clock flag (1) if crystal oscillator is disabled, and (0) ic clock activity is observed Crystal clock signal divided by 4 Crystal clock signal divided by 16 Clock output signal, according to programmed dividers (ckdiv[2:0]) Internal enable signal (OR function of the ENABLE pin and enable bit) SPI mode capacitor setting
frac_fxdb
Fractional-N mode (1) or ASK fixed-N mode (0) ASK digital shaping flag (1) when PA power value is different than 0 Fractional-N 4-bit integer value Fractional-N 12-bit fractional value Transmitter PA enable flag PLL lock-detect flag
capfxd[4:0] Emulation mode variable capacitor setting notover integ[3:0] frac[11:0] xmit_en lockdet
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280MHz to 450MHz Programmable ASK/FSK Transmitter MAX7060
Manual Mode Settings
The MAX7060 can be operated by controlling certain pins directly, thereby eliminating the need for an SPI controller. There is a restricted selection of frequency and power settings, but operation is simpler. The pins that are used in manual mode are as follows: Pin 1: GPO2_MOD (modulation mode, 0 = ASK, 1 = FSK) CS_DEV (FSK deviation selection, 0 = Q16kHz, 1 = Q50kHz) There are seven internally set fractional-N divide ratios that correspond to commonly used frequencies when a 16MHz crystal is used. Notice that the MAX7060 can be operated manually at any single frequency over its 280MHz to 450MHz operating range by choosing a crystal frequency and one of the divide ratios from Table 25. For example, a transmitting frequency of 308MHz can be achieved by selecting the 19.68750 divide ratio and a 15.6444MHz crystal. The frequency settings in the manual mode of operation were designed in a way that allows the customer to toggle only one control line between low and high states to switch between seven commonly used frequency pairs (see Table 26). Reset pin 1 (GPO2_MOD) to 0 for ASK modulation and 1 for FSK modulation. Analog shaping in ASK mode is enabled by using the ROUT pin. The turn-on and turn-off time is fixed at approximately 1s.
Frequency Selection
Pins 5, 6, 7: FREQ0, FREQ1, FREQ2 Pin 19:
Pins 20, 21: SDI_PWR1 and SCLK_PWR0 (2-pin power selection) Pins 22, 23: DIN and ENABLE (PA variable capacitor setting, data input, enable) To put the MAX7060 in manual mode, set any of the FREQ0, FREQ1, FREQ2 pins (5, 6, and 7) to logic-high. These pins are normally pulled down, so the default state of the MAX7060 is for SPI operation. The settings in Table 25 can be made in manual mode.
ASK or FSK Modulation
Table 25. Manual Mode Frequency Selection
FREQ2 0 0 0 0 1 1 1 1 FREQ1 0 0 1 1 0 0 1 1 FREQ0 0 1 0 1 0 1 0 1 FREQUENCY (MHz) SPI 315.00 433.62 390.00 418.00 372.00 345.00 433.92 DIVIDE RATIO N/A 19.68750 27.10125 24.37500 26.12500 23.25000 21.56250 27.12000
Table 26. Manual Mode Frequency Pair Switching
LOW FREQUENCY (MHz) 315.00 418.00 433.62 315.00 315.00 345.00 390.00 HIGH FREQUENCY (MHz) 433.92 433.92 433.92 390.00 372.00 433.92 433.92 FREQ2, FREQ1, FREQ0 001 to 111. Set FREQ0 high, shorting FREQ1 and FREQ2, toggling 1 line. 100 to 111. Set FREQ2 high, shorting FREQ1 and FREQ0, toggling 1 line. 010 to 111. Set FREQ1 high, shorting FREQ2 and FREQ0, toggling 1 line. 001 to 011. Set FREQ0 high and FREQ2 low, toggling FREQ1. 001 to 101. Set FREQ1 low and FREQ0 high, toggling pin FREQ2. 110 to 111. Set FREQ2 and FREQ1 high, toggling FREQ0. 011 to 111. Set FREQ1 and FREQ0 high, toggling FREQ2.
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280MHz to 450MHz Programmable ASK/FSK Transmitter
Table 27. Output Power Settings
SDI_PWR1 0 0 1 1 SCLK_PWR0 0 1 0 1 dB BELOW PMAX 0 3 6 10
set, so that it adds the programmed capacitance to the PA when the chosen frequency is selected. This scheme must be executed only once to set the value of the variable capacitor. For example, a user can operate the MAX7060 at 315MHz and 433.92MHz into a narrowband antenna by resetting the ENABLE pin low, setting the FREQ0, FREQ1, FREQ2 pins to 001 (315MHz), and sending the appropriate number of pulses into the DIN pin, and then setting the ENABLE pin high. When the frequency is set to 433.92MHz (or any other frequency in the table except 315MHz), no capacitance is added to the PA output. When the frequency is set to 315MHz, the PA capacitance increases by the programmed value. Figure 8 illustrates how to set the capacitance. It begins with the ENABLE pin pulled low. The frequency is sampled at the rising edge of the first pulse. Pulses 2-11 set the capacitance code to 0x0A (10dec), which is approximately 2.5pF. The ENABLE pin is then pulled high to finish the setting.
MAX7060
ENABLE FREQ[2:0] DIN CAP CODE CAPTURED CAP VALUE X 0x0A X 0x1
Figure 8. Variable Capacitor Setting Timing Diagram
Emulation Mode Settings
All the settings available through the manual mode of operation are also easily accessible in the SPI mode. This mode is called emulation mode, whereby only writing one or two registers, the whole transmitter can be configured. The Conf2 register controls this mode. The emulation mode is a subset of SPI mode. It gives SPI users the capability to operate the part by programming just one or two registers instead of all registers. Since it is still SPI mode, pins 5, 6, and 7 (FREQ0, FREQ1, and FREQ2) must be pulled low. The Conf2 register is the only register that needs to be programmed. Setting bit 7 (fixed) to 1 enables this mode. Bit 6 (fxmode) is equivalent to pin 1 (GPO2_MOD) in manual mode. Bits 5 and 4 (fxpwr[1:0]) are equivalent to pin 20 and 21 (SDI_PWR1 and SCLK_PWR0) in manual mode. Bit 3 (fxhdev) is equivalent to pin 19 (CS_DEV) in manual mode. Bits 2, 1, and 0 (fxfrq[2:0]) are equivalent to pins 5, 6, and 7 (FREQ0, FREQ1, and FREQ2) in manual mode. Similar to manual mode, the PA capacitor setting in the emulation mode can be done by toggling the DIN pin with the ENABLE pin low. In addition, the capacitor setting can also be done by directly writing to the capacitor register (bits 4:0 of the Conf1 register, cap[4:0]). As long as the capacitor register value is not zero, the capacitor value sent in by toggling the DIN pin is ignored.
Reset pin 19 (CS_DEV) to 0 for 32kHz (Q16kHz) FSK deviation and 1 for 100kHz (Q50kHz) FSK deviation. Set SDI_PWR1 (pin 20) and SCLK_PWR0 (pin 21) to four power settings (relative to the maximum power setting). Note that at battery voltages below 3V, the top two power settings are compressed and the power difference is less than 3dB.
Frequency Deviation
Transmitter Power
In manual mode, capacitance can be added to the PA output for one selected frequency. This allows the user to adjust the matching network when switching between two frequencies in the manual selection table, or for switching to one frequency that is significantly different from the others in the table. The user can set the capacitance by resetting the ENABLE pin to a logic-low, then selecting the frequency for which the variable capacitor is to be added from the seven possible settings, and then sending a stream of 1 to 32 pulses through the DIN pin. The first pulse is used to reset the internal capacitor counter and to latch the selected frequency. After the first pulse, the remaining number of pulses sent equals the variable capacitor setting. When the ENABLE pin goes high, the capacitor setting for the specified frequency is
PA Variable Capacitor Setting
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27
280MHz to 450MHz Programmable ASK/FSK Transmitter MAX7060
Typical Application Circuits
SPI Mode (5V Supply)
C1 Y1 C4 +3VREG +5V C7 13 PAVOUT ROUT 12 +3VREG SDI_PWR1 SCLK_PWR0 ENABLE DIN N.C. GPO2_MOD 1 GPO1 2 +3VREG C12 DVDD GPOVDD 3 4 C11 +5V PAVDD 11 C9 C10 MATCHING NETWORK COMPONENTS Tx ANTENNA L1 C8
C2 18 XTAL1 19 20 21 22 DIGITAL CONTROLLER 23 24 CS_DEV
C3 17 XTAL2 16
C5 15 14
C6
AVDD
N.C. VDD5
MAX7060
PAOUT N.C. LSHDN FREQ2 FREQ0 FREQ1 5 6
10 9 8 7
Manual Mode (3V Supply, Shaped ASK Modulation, 315MHz)
C1 Y1 C4 +3V C5 16 AVDD 15 14 +3V C6 13 PAVOUT ROUT 12 +3V 11 C9 C10 L1 C8 Tx ANTENNA MATCHING NETWORK COMPONENTS C7
C2 18 XTAL1 19 20 21 22 23 24 DIGITAL CONTROLLER CS_DEV SDI_PWR1 SCLK_PWR0
C3 17 XTAL2
N.C. VDD5
PAVDD
MAX7060
ENABLE DIN N.C. GPO2_MOD 1 GPO1 2 C12 DVDD 3 GPOVDD 4 +3V C11 FREQ0 5 PAOUT N.C. LSHDN FREQ2 FREQ1 6 10 9 8 7
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280MHz to 450MHz Programmable ASK/FSK Transmitter
Component Lists
SPI Mode (5V Supply)
DESIGNATION C1, C4 C2, C3 C5, C6 C7, C8, C9 C10, C11, C12 L1 Matching Network Components U1 Y1 QTY 2 2 2 3 3 1 4 1 1 DESCRIPTION Not needed if crystal load capacitance is 8pF 1.5nF 10%, 50V X7R ceramic capacitors (0603) Murata GRM188R71H152K 100nF 10%, 50V X7R ceramic capacitors (0603) Murata GRM188R71H104K 220pF 5% ceramic capacitors (0603) Murata GRM1885C1H220JA01D 10nF 10%, 50V X7R ceramic capacitors (0603) Murata GRM188R71H103K 5% wire-wound inductor (0603) Murata LQW18 series (value depends on matching network) 3 capacitors and 1 inductor (values depend on frequency range and antenna impedance) Maxim MAX7060ATG+ 16MHz crystal Crystek 17466 Suntsu SCX284
MAX7060
Manual Mode (3V Supply)
DESIGNATION C1, C4 C2, C3 C5, C6 C7, C8, C9 C10, C11, C12 L1 Matching Network Components U1 Y1 QTY 2 2 2 3 3 1 4 1 1 DESCRIPTION Not needed if crystal load capacitance is 8pF 1.5nF 10%, 50V X7R ceramic capacitors (0603) Murata GRM188R71H152K 100nF 10%, 50V X7R ceramic capacitors (0603) Murata GRM188R71H104K 220pF 5% ceramic capacitors (0603) Murata GRM1885C1H220JA01D 10nF 10%, 50V X7R ceramic capacitors (0603) Murata GRM188R71H103K 5% wire-wound inductor (0603) Murata LQW18 series (value depends on matching network) 3 Capacitors and 1 Inductor. Values depend on frequency range and antenna impedance. Maxim MAX7060ATG+ 16MHz crystal Crystek 17466 Suntsu SCX284
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29
280MHz to 450MHz Programmable ASK/FSK Transmitter MAX7060
Chip Information
PROCESS: CMOS
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE 24 TQFN-EP PACKAGE CODE T2444+3 DOCUMENT NO. 21-0139
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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(c)
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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